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VGA: cleanup pmod errors and top design somewhat

This commit is contained in:
Peder Bergebakken Sundt 2020-08-19 16:33:41 +02:00
parent 21ab8a5a93
commit 8d2c12225b
4 changed files with 61 additions and 51 deletions
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2
fpga/icebreaker.dg
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@ -14,7 +14,7 @@ Top = subclass Elaboratable where
@ledg = platform.request "led_g" 0 @ledg = platform.request "led_g" 0
@seg7 = platform.request "seven_seg" @seg7 = platform.request "seven_seg"
blinker = (Submodule.blinker$ Blinker$ freq // 3 ).out blinker = (Submodule.blinker$ Blinker$ freq // 3).out
pulser = (Submodule.pulser $ Pulser$ freq // 2).out pulser = (Submodule.pulser $ Pulser$ freq // 2).out
seg7 = Submodule.seg7$ Segment7x2 decimal: False seg7 = Submodule.seg7$ Segment7x2 decimal: False

25
fpga/icebreaker_vga.dg
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@ -40,22 +40,21 @@ run_icepll = current target ->
Top = subclass Elaboratable where Top = subclass Elaboratable where
__init__ = x y ~> None where __init__ = x y fps ~> None where
@x = x @x, @y, @fps = x, y, fps
@y = y
elaborate = platform ~> m where with m = Module! => elaborate = platform ~> m where with m = Module! =>
# Configure DVI controller # Configure DVI controller
dvi = Submodule$ DviController12 @x @y fps:60 dvi = Submodule.dvi$ DviController12 @x @y @fps
# setup clock # setup PLL clock
default_clk = platform.request platform.default_clk dir:"-" default_clk = platform.request platform.default_clk dir:"-"
default_freq = platform.default_clk_frequency default_freq = platform.default_clk_frequency
default_reset = if default_reset = if
platform.default_rst => platform.request platform.default_rst platform.default_rst => platform.request platform.default_rst
otherwise => Const 1 otherwise => Const 0
pll_config = run_icepll pll_config = run_icepll
default_freq default_freq
@ -64,10 +63,10 @@ Top = subclass Elaboratable where
print pll_config print pll_config
pll_clk, pll_lock = Signal!, Signal! pll_clk, pll_lock = Signal!, Signal!
Submodule.pll$ Instance "SB_PLL40_PAD" # "SB_PLL40_CORE" Submodule.pll$ Instance "SB_PLL40_PAD" # or "SB_PLL40_CORE"
i_PACKAGEPIN : default_clk # i_REFERENCECLK i_PACKAGEPIN : default_clk # or i_REFERENCECLK
i_BYPASS : (Const 0) i_BYPASS : (Const 0)
i_RESETB : default_reset i_RESETB : ~default_reset
o_LOCK : pll_lock o_LOCK : pll_lock
o_PLLOUTGLOBAL : pll_clk o_PLLOUTGLOBAL : pll_clk
p_FEEDBACK_PATH : pll_config.FEEDBACK p_FEEDBACK_PATH : pll_config.FEEDBACK
@ -88,7 +87,7 @@ Top = subclass Elaboratable where
scroll = Signal 8 scroll = Signal 8
period = int (pll_config.achieved / 60) period = int$ pll_config.achieved / @fps
counter = Signal$ range period counter = Signal$ range period
Sync$ counter ::= counter - 1 Sync$ counter ::= counter - 1
When (counter==0) $ -> When (counter==0) $ ->
@ -100,8 +99,8 @@ Top = subclass Elaboratable where
Sync$ dvi.b ::= 0x0 Sync$ dvi.b ::= 0x0
cx = to_signed dvi.pixel_x - (@x // 2) cx = to_signed dvi.pixel_x - (@x // 2)
cy = to_signed dvi.pixel_y - (@y // 2) cy = to_signed dvi.pixel_y - (@y // 2)
rx = cx*cx rx = cx * cx
ry = cy*cy ry = cy * cy
tx1 = (dvi.pixel_x - scroll ) & (1<<5) tx1 = (dvi.pixel_x - scroll ) & (1<<5)
ty1 = (dvi.pixel_y - scroll ) & (1<<5) ty1 = (dvi.pixel_y - scroll ) & (1<<5)
tx2 = (dvi.pixel_x + scroll ) & (1<<6) tx2 = (dvi.pixel_x + scroll ) & (1<<6)
@ -111,8 +110,10 @@ Top = subclass Elaboratable where
Sync$ dvi.r ::= 0xF Sync$ dvi.r ::= 0xF
#Sync$ dvi.g ::= 0xF #Sync$ dvi.g ::= 0xF
Sync$ dvi.b ::= 0xF Sync$ dvi.b ::= 0xF
tx1 ^ ty1 ,-> tx1 ^ ty1 ,->
Sync$ dvi.b ::= 0xF Sync$ dvi.b ::= 0xF
tx2 ^ ty2 ,-> tx2 ^ ty2 ,->
Sync$ dvi.r ::= 0xF Sync$ dvi.r ::= 0xF
Sync$ dvi.g ::= 0xF Sync$ dvi.g ::= 0xF

46
fpga/modules/vga.dg
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@ -7,6 +7,24 @@ import "/warnings/warn"
import "../common/pipeline" import "../common/pipeline"
import "../resources/pmod" import "../resources/pmod"
# graph shamelessly stolen from gtf.c
# https://linux.die.net/man/1/gtf
#
# <--------1--------> <--2--> <--3--> <--4-->
# _________
# |-------------------|_______| |_______
#
# R SS SE FL
# 1: 'active' - visible image
# 2: 'front' - blank before sync (aka front porch)
# 3: 'sync' - sync pulse
# 4: 'back' - blank after sync (aka back porch)
# R: Resolution
# SS: Sync Start
# SE: Sync End
# FL: Frame Length
# total_x = front_x + sync_x + back_x + active_x # total_x = front_x + sync_x + back_x + active_x
# total_y = front_y + sync_y + back_y + active_x # total_y = front_y + sync_y + back_y + active_x
# pix_freq = total_x * total_y * fps # pix_freq = total_x * total_y * fps
@ -38,7 +56,6 @@ VGA_TIMINGS = dict' # VGA, SVGA, VESA
# http://martin.hinner.info/vga/timing.html # http://martin.hinner.info/vga/timing.html
# https://linux.die.net/man/1/gtf
run_gtf = x y fps -> run_gtf = x y fps ->
out = subprocess.run ["gtf", str x, str y, str fps, "-x"] out = subprocess.run ["gtf", str x, str y, str fps, "-x"]
capture_output: True capture_output: True
@ -55,33 +72,10 @@ run_gtf = x y fps ->
bind take 8 bind take 8
bind map int bind map int
# <--------1--------> <--2--> <--3--> <--4--> # front_x, sync_x, back_x, front_y, sync_y, back_y
# _________
# |-------------------|_______| |_______
#
# R SS SE FL
# 1: visible image
# 2: blank before sync (aka front porch)
# 3: sync pulse
# 4: blank after sync (aka back porch)
# R: Resolution
# SS: Sync Start
# SE: Sync End
# FL: Frame Length
#total_x, active_x, front_x, sync_x, back_x = hfl, hr, hss-hr, hse-hss, hfl-hse
#total_y, active_y, front_y, sync_y, back_y = vfl, vr, vss-vr, vse-vss, vfl-vse
#print hr hss hse hfl
#print vr vss vse vfl
#print active_x front_x sync_x back_x total_x sep:"\t"
#print active_y front_y sync_y back_y total_x sep:"\t"
#return (front_x, sync_x, back_x, front_y, sync_y, back_y)
hss-hr, hse-hss, hfl-hse, vss-vr, vse-vss, vfl-vse hss-hr, hse-hss, hfl-hse, vss-vr, vse-vss, vfl-vse
VgaController = subclass Elaboratable where VgaController = subclass Elaboratable where
__init__ = x y fps bitwidth resource_name resource_number: 0 ~> None where __init__ = x y fps bitwidth resource_name resource_number: 0 ~> None where
# params # params
@ -179,7 +173,7 @@ if __name__ == "__main__" =>
list' list'
design.pixel_x design.pixel_x
design.pixel_y design.pixel_y
design.ack design.active
design.r design.r
design.g design.g
design.b design.b

39
fpga/resources/pmod.py
View File

@ -42,26 +42,41 @@ def dip_switch8(number, *, pmod, name=__name__, subsignal_args=(), extras={}):
@pmod @pmod
def dvi_3bit(number, *, pmod1=0, pmod2=1, name=__name__, subsignal_args=(), extras={}): def dvi_3bit(number, *, pmod, name=__name__, subsignal_args=(), extras={}):
# 3b PMOD Connector - Facing module pins
# ----------------------------
# | 1-G 3-CK 5-HS 7-NC GND 3V |
# | 0-R 2-B 4-DE 6-VS GND 3V |
# ___|____________________________|___
# | BML HDMI 3b color PMOD board |
# ------------------------------------
return [Resource(name, number, return [Resource(name, number,
Subsignal("r", Pins (" 1", dir="o", conn=("pmod", pmod1)), *subsignal_args), # red Subsignal("r", Pins (" 7", dir="o", conn=("pmod", pmod)), *subsignal_args), # red
Subsignal("g", Pins (" 2", dir="o", conn=("pmod", pmod1)), *subsignal_args), # green Subsignal("g", Pins (" 1", dir="o", conn=("pmod", pmod)), *subsignal_args), # green
Subsignal("b", Pins (" 3", dir="o", conn=("pmod", pmod2)), *subsignal_args), # blue Subsignal("b", Pins (" 8", dir="o", conn=("pmod", pmod)), *subsignal_args), # blue
Subsignal("ck", Pins (" 4", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data clock Subsignal("ck", Pins (" 2", dir="o", conn=("pmod", pmod)), *subsignal_args), # data clock
Subsignal("de", Pins (" 7", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data enable Subsignal("de", Pins (" 9", dir="o", conn=("pmod", pmod)), *subsignal_args), # data enable
Subsignal("hs", Pins (" 8", dir="o", conn=("pmod", pmod2)), *subsignal_args), # hsync Subsignal("hs", Pins (" 3", dir="o", conn=("pmod", pmod)), *subsignal_args), # hsync
Subsignal("vs", Pins (" 9", dir="o", conn=("pmod", pmod2)), *subsignal_args), # vsync Subsignal("vs", Pins ("10", dir="o", conn=("pmod", pmod)), *subsignal_args), # vsync
#Subsignal("", Pins ("10", dir="o", conn=("pmod", pmod2)), *subsignal_args), #Subsignal("", Pins (" 4", dir="o", conn=("pmod", pmod)), *subsignal_args),
**extras, **extras,
)] )]
@pmod @pmod
def dvi_12bit(number, *, pmod1=0, pmod2=1, name=__name__, subsignal_args=(), extras={}): def dvi_12bit(number, *, pmod1=0, pmod2=1, name=__name__, subsignal_args=(), extras={}):
# 12b Module - Facing PMOD pins
# J0 J1
# ---------------------------- ----------------------------
# | 1-R3 3-R1 5-G3 7-G1 GND 3V | | 1-B3 3-ck 5-B0 7-HS GND 3V |
# | 0-R2 2-R0 4-G2 6-G0 GND 3V | | 0-B2 2-B1 4-DE 6-VS GND 3V |
# ___|____________________________|______|____________________________|__
# | BML HDMI 12b color PMOD board |
# -----------------------------------------------------------------------
return [Resource(name, number, return [Resource(name, number,
Subsignal("r", Pins (" 8 7 2 1", dir="o", conn=("pmod", pmod1)), *subsignal_args), # red Subsignal("r", Pins (" 8 2 7 1", dir="o", conn=("pmod", pmod1)), *subsignal_args), # red
Subsignal("g", Pins ("10 9 4 3", dir="o", conn=("pmod", pmod1)), *subsignal_args), # green Subsignal("g", Pins ("10 4 9 3", dir="o", conn=("pmod", pmod1)), *subsignal_args), # green
Subsignal("b", Pins (" 3 7 8 1", dir="o", conn=("pmod", pmod2)), *subsignal_args), # blue Subsignal("b", Pins (" 3 8 7 1", dir="o", conn=("pmod", pmod2)), *subsignal_args), # blue
Subsignal("ck", Pins (" 2", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data clock Subsignal("ck", Pins (" 2", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data clock
Subsignal("de", Pins (" 9", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data enable Subsignal("de", Pins (" 9", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data enable
Subsignal("hs", PinsN(" 4", dir="o", conn=("pmod", pmod2)), *subsignal_args), # hsync Subsignal("hs", PinsN(" 4", dir="o", conn=("pmod", pmod2)), *subsignal_args), # hsync