From 8d2c12225b1b2657dc7b3a589e9a87d24d9e3717 Mon Sep 17 00:00:00 2001 From: Peder Bergebakken Sundt Date: Wed, 19 Aug 2020 16:33:41 +0200 Subject: [PATCH] VGA: cleanup pmod errors and top design somewhat --- fpga/icebreaker.dg | 2 +- fpga/icebreaker_vga.dg | 25 ++++++++++++----------- fpga/modules/vga.dg | 46 ++++++++++++++++++------------------------ fpga/resources/pmod.py | 39 ++++++++++++++++++++++++----------- 4 files changed, 61 insertions(+), 51 deletions(-) diff --git a/fpga/icebreaker.dg b/fpga/icebreaker.dg index 5b27af9..74a57a9 100644 --- a/fpga/icebreaker.dg +++ b/fpga/icebreaker.dg @@ -14,7 +14,7 @@ Top = subclass Elaboratable where @ledg = platform.request "led_g" 0 @seg7 = platform.request "seven_seg" - blinker = (Submodule.blinker$ Blinker$ freq // 3 ).out + blinker = (Submodule.blinker$ Blinker$ freq // 3).out pulser = (Submodule.pulser $ Pulser$ freq // 2).out seg7 = Submodule.seg7$ Segment7x2 decimal: False diff --git a/fpga/icebreaker_vga.dg b/fpga/icebreaker_vga.dg index 9ea5ccb..2033581 100644 --- a/fpga/icebreaker_vga.dg +++ b/fpga/icebreaker_vga.dg @@ -40,22 +40,21 @@ run_icepll = current target -> Top = subclass Elaboratable where - __init__ = x y ~> None where - @x = x - @y = y + __init__ = x y fps ~> None where + @x, @y, @fps = x, y, fps elaborate = platform ~> m where with m = Module! => # Configure DVI controller - dvi = Submodule$ DviController12 @x @y fps:60 + dvi = Submodule.dvi$ DviController12 @x @y @fps - # setup clock + # setup PLL clock default_clk = platform.request platform.default_clk dir:"-" default_freq = platform.default_clk_frequency default_reset = if platform.default_rst => platform.request platform.default_rst - otherwise => Const 1 + otherwise => Const 0 pll_config = run_icepll default_freq @@ -64,10 +63,10 @@ Top = subclass Elaboratable where print pll_config pll_clk, pll_lock = Signal!, Signal! - Submodule.pll$ Instance "SB_PLL40_PAD" # "SB_PLL40_CORE" - i_PACKAGEPIN : default_clk # i_REFERENCECLK + Submodule.pll$ Instance "SB_PLL40_PAD" # or "SB_PLL40_CORE" + i_PACKAGEPIN : default_clk # or i_REFERENCECLK i_BYPASS : (Const 0) - i_RESETB : default_reset + i_RESETB : ~default_reset o_LOCK : pll_lock o_PLLOUTGLOBAL : pll_clk p_FEEDBACK_PATH : pll_config.FEEDBACK @@ -88,7 +87,7 @@ Top = subclass Elaboratable where scroll = Signal 8 - period = int (pll_config.achieved / 60) + period = int$ pll_config.achieved / @fps counter = Signal$ range period Sync$ counter ::= counter - 1 When (counter==0) $ -> @@ -100,8 +99,8 @@ Top = subclass Elaboratable where Sync$ dvi.b ::= 0x0 cx = to_signed dvi.pixel_x - (@x // 2) cy = to_signed dvi.pixel_y - (@y // 2) - rx = cx*cx - ry = cy*cy + rx = cx * cx + ry = cy * cy tx1 = (dvi.pixel_x - scroll ) & (1<<5) ty1 = (dvi.pixel_y - scroll ) & (1<<5) tx2 = (dvi.pixel_x + scroll ) & (1<<6) @@ -111,8 +110,10 @@ Top = subclass Elaboratable where Sync$ dvi.r ::= 0xF #Sync$ dvi.g ::= 0xF Sync$ dvi.b ::= 0xF + tx1 ^ ty1 ,-> Sync$ dvi.b ::= 0xF + tx2 ^ ty2 ,-> Sync$ dvi.r ::= 0xF Sync$ dvi.g ::= 0xF diff --git a/fpga/modules/vga.dg b/fpga/modules/vga.dg index b488232..4af020d 100644 --- a/fpga/modules/vga.dg +++ b/fpga/modules/vga.dg @@ -7,6 +7,24 @@ import "/warnings/warn" import "../common/pipeline" import "../resources/pmod" + +# graph shamelessly stolen from gtf.c +# https://linux.die.net/man/1/gtf +# +# <--------1--------> <--2--> <--3--> <--4--> +# _________ +# |-------------------|_______| |_______ +# +# R SS SE FL +# 1: 'active' - visible image +# 2: 'front' - blank before sync (aka front porch) +# 3: 'sync' - sync pulse +# 4: 'back' - blank after sync (aka back porch) +# R: Resolution +# SS: Sync Start +# SE: Sync End +# FL: Frame Length + # total_x = front_x + sync_x + back_x + active_x # total_y = front_y + sync_y + back_y + active_x # pix_freq = total_x * total_y * fps @@ -38,7 +56,6 @@ VGA_TIMINGS = dict' # VGA, SVGA, VESA # http://martin.hinner.info/vga/timing.html -# https://linux.die.net/man/1/gtf run_gtf = x y fps -> out = subprocess.run ["gtf", str x, str y, str fps, "-x"] capture_output: True @@ -55,33 +72,10 @@ run_gtf = x y fps -> bind take 8 bind map int - # <--------1--------> <--2--> <--3--> <--4--> - # _________ - # |-------------------|_______| |_______ - # - # R SS SE FL - # 1: visible image - # 2: blank before sync (aka front porch) - # 3: sync pulse - # 4: blank after sync (aka back porch) - # R: Resolution - # SS: Sync Start - # SE: Sync End - # FL: Frame Length - - #total_x, active_x, front_x, sync_x, back_x = hfl, hr, hss-hr, hse-hss, hfl-hse - #total_y, active_y, front_y, sync_y, back_y = vfl, vr, vss-vr, vse-vss, vfl-vse - #print hr hss hse hfl - #print vr vss vse vfl - #print active_x front_x sync_x back_x total_x sep:"\t" - #print active_y front_y sync_y back_y total_x sep:"\t" - #return (front_x, sync_x, back_x, front_y, sync_y, back_y) - + # front_x, sync_x, back_x, front_y, sync_y, back_y hss-hr, hse-hss, hfl-hse, vss-vr, vse-vss, vfl-vse - - VgaController = subclass Elaboratable where __init__ = x y fps bitwidth resource_name resource_number: 0 ~> None where # params @@ -179,7 +173,7 @@ if __name__ == "__main__" => list' design.pixel_x design.pixel_y - design.ack + design.active design.r design.g design.b diff --git a/fpga/resources/pmod.py b/fpga/resources/pmod.py index 11fa748..cceb56b 100644 --- a/fpga/resources/pmod.py +++ b/fpga/resources/pmod.py @@ -42,26 +42,41 @@ def dip_switch8(number, *, pmod, name=__name__, subsignal_args=(), extras={}): @pmod -def dvi_3bit(number, *, pmod1=0, pmod2=1, name=__name__, subsignal_args=(), extras={}): +def dvi_3bit(number, *, pmod, name=__name__, subsignal_args=(), extras={}): + # 3b PMOD Connector - Facing module pins + # ---------------------------- + # | 1-G 3-CK 5-HS 7-NC GND 3V | + # | 0-R 2-B 4-DE 6-VS GND 3V | + # ___|____________________________|___ + # | BML HDMI 3b color PMOD board | + # ------------------------------------ return [Resource(name, number, - Subsignal("r", Pins (" 1", dir="o", conn=("pmod", pmod1)), *subsignal_args), # red - Subsignal("g", Pins (" 2", dir="o", conn=("pmod", pmod1)), *subsignal_args), # green - Subsignal("b", Pins (" 3", dir="o", conn=("pmod", pmod2)), *subsignal_args), # blue - Subsignal("ck", Pins (" 4", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data clock - Subsignal("de", Pins (" 7", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data enable - Subsignal("hs", Pins (" 8", dir="o", conn=("pmod", pmod2)), *subsignal_args), # hsync - Subsignal("vs", Pins (" 9", dir="o", conn=("pmod", pmod2)), *subsignal_args), # vsync - #Subsignal("", Pins ("10", dir="o", conn=("pmod", pmod2)), *subsignal_args), + Subsignal("r", Pins (" 7", dir="o", conn=("pmod", pmod)), *subsignal_args), # red + Subsignal("g", Pins (" 1", dir="o", conn=("pmod", pmod)), *subsignal_args), # green + Subsignal("b", Pins (" 8", dir="o", conn=("pmod", pmod)), *subsignal_args), # blue + Subsignal("ck", Pins (" 2", dir="o", conn=("pmod", pmod)), *subsignal_args), # data clock + Subsignal("de", Pins (" 9", dir="o", conn=("pmod", pmod)), *subsignal_args), # data enable + Subsignal("hs", Pins (" 3", dir="o", conn=("pmod", pmod)), *subsignal_args), # hsync + Subsignal("vs", Pins ("10", dir="o", conn=("pmod", pmod)), *subsignal_args), # vsync + #Subsignal("", Pins (" 4", dir="o", conn=("pmod", pmod)), *subsignal_args), **extras, )] @pmod def dvi_12bit(number, *, pmod1=0, pmod2=1, name=__name__, subsignal_args=(), extras={}): + # 12b Module - Facing PMOD pins + # J0 J1 + # ---------------------------- ---------------------------- + # | 1-R3 3-R1 5-G3 7-G1 GND 3V | | 1-B3 3-ck 5-B0 7-HS GND 3V | + # | 0-R2 2-R0 4-G2 6-G0 GND 3V | | 0-B2 2-B1 4-DE 6-VS GND 3V | + # ___|____________________________|______|____________________________|__ + # | BML HDMI 12b color PMOD board | + # ----------------------------------------------------------------------- return [Resource(name, number, - Subsignal("r", Pins (" 8 7 2 1", dir="o", conn=("pmod", pmod1)), *subsignal_args), # red - Subsignal("g", Pins ("10 9 4 3", dir="o", conn=("pmod", pmod1)), *subsignal_args), # green - Subsignal("b", Pins (" 3 7 8 1", dir="o", conn=("pmod", pmod2)), *subsignal_args), # blue + Subsignal("r", Pins (" 8 2 7 1", dir="o", conn=("pmod", pmod1)), *subsignal_args), # red + Subsignal("g", Pins ("10 4 9 3", dir="o", conn=("pmod", pmod1)), *subsignal_args), # green + Subsignal("b", Pins (" 3 8 7 1", dir="o", conn=("pmod", pmod2)), *subsignal_args), # blue Subsignal("ck", Pins (" 2", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data clock Subsignal("de", Pins (" 9", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data enable Subsignal("hs", PinsN(" 4", dir="o", conn=("pmod", pmod2)), *subsignal_args), # hsync