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VGA: cleanup pmod errors and top design somewhat

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Peder Bergebakken Sundt
2020-08-19 16:33:41 +02:00
parent 21ab8a5a93
commit 8d2c12225b
4 changed files with 61 additions and 51 deletions
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39
fpga/resources/pmod.py
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@@ -42,26 +42,41 @@ def dip_switch8(number, *, pmod, name=__name__, subsignal_args=(), extras={}):
@pmod
def dvi_3bit(number, *, pmod1=0, pmod2=1, name=__name__, subsignal_args=(), extras={}):
def dvi_3bit(number, *, pmod, name=__name__, subsignal_args=(), extras={}):
# 3b PMOD Connector - Facing module pins
# ----------------------------
# | 1-G 3-CK 5-HS 7-NC GND 3V |
# | 0-R 2-B 4-DE 6-VS GND 3V |
# ___|____________________________|___
# | BML HDMI 3b color PMOD board |
# ------------------------------------
return [Resource(name, number,
Subsignal("r", Pins (" 1", dir="o", conn=("pmod", pmod1)), *subsignal_args), # red
Subsignal("g", Pins (" 2", dir="o", conn=("pmod", pmod1)), *subsignal_args), # green
Subsignal("b", Pins (" 3", dir="o", conn=("pmod", pmod2)), *subsignal_args), # blue
Subsignal("ck", Pins (" 4", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data clock
Subsignal("de", Pins (" 7", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data enable
Subsignal("hs", Pins (" 8", dir="o", conn=("pmod", pmod2)), *subsignal_args), # hsync
Subsignal("vs", Pins (" 9", dir="o", conn=("pmod", pmod2)), *subsignal_args), # vsync
#Subsignal("", Pins ("10", dir="o", conn=("pmod", pmod2)), *subsignal_args),
Subsignal("r", Pins (" 7", dir="o", conn=("pmod", pmod)), *subsignal_args), # red
Subsignal("g", Pins (" 1", dir="o", conn=("pmod", pmod)), *subsignal_args), # green
Subsignal("b", Pins (" 8", dir="o", conn=("pmod", pmod)), *subsignal_args), # blue
Subsignal("ck", Pins (" 2", dir="o", conn=("pmod", pmod)), *subsignal_args), # data clock
Subsignal("de", Pins (" 9", dir="o", conn=("pmod", pmod)), *subsignal_args), # data enable
Subsignal("hs", Pins (" 3", dir="o", conn=("pmod", pmod)), *subsignal_args), # hsync
Subsignal("vs", Pins ("10", dir="o", conn=("pmod", pmod)), *subsignal_args), # vsync
#Subsignal("", Pins (" 4", dir="o", conn=("pmod", pmod)), *subsignal_args),
**extras,
)]
@pmod
def dvi_12bit(number, *, pmod1=0, pmod2=1, name=__name__, subsignal_args=(), extras={}):
# 12b Module - Facing PMOD pins
# J0 J1
# ---------------------------- ----------------------------
# | 1-R3 3-R1 5-G3 7-G1 GND 3V | | 1-B3 3-ck 5-B0 7-HS GND 3V |
# | 0-R2 2-R0 4-G2 6-G0 GND 3V | | 0-B2 2-B1 4-DE 6-VS GND 3V |
# ___|____________________________|______|____________________________|__
# | BML HDMI 12b color PMOD board |
# -----------------------------------------------------------------------
return [Resource(name, number,
Subsignal("r", Pins (" 8 7 2 1", dir="o", conn=("pmod", pmod1)), *subsignal_args), # red
Subsignal("g", Pins ("10 9 4 3", dir="o", conn=("pmod", pmod1)), *subsignal_args), # green
Subsignal("b", Pins (" 3 7 8 1", dir="o", conn=("pmod", pmod2)), *subsignal_args), # blue
Subsignal("r", Pins (" 8 2 7 1", dir="o", conn=("pmod", pmod1)), *subsignal_args), # red
Subsignal("g", Pins ("10 4 9 3", dir="o", conn=("pmod", pmod1)), *subsignal_args), # green
Subsignal("b", Pins (" 3 8 7 1", dir="o", conn=("pmod", pmod2)), *subsignal_args), # blue
Subsignal("ck", Pins (" 2", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data clock
Subsignal("de", Pins (" 9", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data enable
Subsignal("hs", PinsN(" 4", dir="o", conn=("pmod", pmod2)), *subsignal_args), # hsync