Peder Bergebakken Sundt 5702101d03 wip

2023-07-08 02:59:40 +02:00

..

__init__.py

Move the iCE40 pll logic to a separate file

2020-08-19 23:20:55 +02:00

i2c.py

wip

2023-07-08 02:59:40 +02:00

i2s.py

wip

2023-07-08 02:59:40 +02:00

ice40pll.dg

Fix off-by-one error in vga.dg and add vga.{h,v}blank_begin signals

2020-08-20 01:15:28 +02:00

rom.py

wip

2023-07-08 02:59:40 +02:00

spi.py

wip

2023-07-08 02:59:40 +02:00