Move the iCE40 pll logic to a separate file
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@ -1,43 +1,12 @@
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import "/collections/namedtuple"
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import "/nmigen/lib/cdc/ResetSynchronizer"
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import "/nmigen_boards.icebreaker/ICEBreakerPlatform"
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import "/nmigen_dg/*"
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import "/subprocess"
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import "/sys"
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import "common/pipeline"
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import "common/to_signed"
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import "modules/vga/DviController12"
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import "stdio/ice40pll/add_domain_from_pll"
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import "resources/pmod"
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run_icepll = current target ->
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current /= 1e6 # Hz -> MHz
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target /= 1e6 # Hz -> MHz
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out = subprocess.run ["icepll", "-i", str current, "-o", str target]
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capture_output: True
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check: True
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get_field = field substring:None ->
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pipeline out.stdout.decode!.splitlines!
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bind filter $ x -> x.startswith field
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if
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substring => bind filter $ x -> substring in x
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otherwise => x -> x # nop
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head
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str.split
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tail
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head
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(namedtuple "icepll_config" "FEEDBACK FILTER_RANGE DIVR DIVF DIVQ given requested achieved")
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str$ get_field "FEEDBACK"
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int$ get_field "FILTER_RANGE"
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int$ get_field "DIVR"
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int$ get_field "DIVF"
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int$ get_field "DIVQ"
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(*) 1e6 $ float $ get_field "F_PLLIN"
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(*) 1e6 $ float $ get_field "F_PLLOUT" "(requested)"
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(*) 1e6 $ float $ get_field "F_PLLOUT" "(achieved)"
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Top = subclass Elaboratable where
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__init__ = x y fps ~> None where
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@ -48,39 +17,8 @@ Top = subclass Elaboratable where
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# Configure DVI controller
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dvi = Submodule.dvi$ DviController12 @x @y @fps
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# setup PLL clock
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default_clk = platform.request platform.default_clk dir:"-"
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default_freq = platform.default_clk_frequency
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default_reset = if
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platform.default_rst => platform.request platform.default_rst
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otherwise => Const 0
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pll_config = run_icepll
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default_freq
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dvi.pix_freq
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print dvi.timings
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print pll_config
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pll_clk, pll_lock = Signal!, Signal!
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Submodule.pll$ Instance "SB_PLL40_PAD" # or "SB_PLL40_CORE"
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i_PACKAGEPIN : default_clk # or i_REFERENCECLK
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i_BYPASS : (Const 0)
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i_RESETB : ~default_reset
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o_LOCK : pll_lock
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o_PLLOUTGLOBAL : pll_clk
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p_FEEDBACK_PATH : pll_config.FEEDBACK
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p_FILTER_RANGE : pll_config.FILTER_RANGE
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p_DIVR : pll_config.DIVR
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p_DIVF : pll_config.DIVF
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p_DIVQ : pll_config.DIVQ
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Domains.sync = ClockDomain "sync"
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Comb$ ClockSignal "sync" ::= pll_clk
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Submodule.rs$ ResetSynchronizer
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~pll_lock
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domain: "sync"
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# setup clock
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pll_config = add_domain_from_pll platform dvi.pix_freq
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# Feed a picture to the DVI controller
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@ -0,0 +1,68 @@
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import "/collections/namedtuple"
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import "/nmigen/lib/cdc/ResetSynchronizer"
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import "/nmigen_dg/*"
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import "/subprocess"
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import "../common/pipeline"
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run_icepll = current target ->
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current /= 1e6 # Hz -> MHz
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target /= 1e6 # Hz -> MHz
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out = subprocess.run ["icepll", "-i", str current, "-o", str target]
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capture_output: True
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check: True
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get_field = field substring:None ->
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pipeline out.stdout.decode!.splitlines!
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bind filter $ x -> x.startswith field
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if
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substring => bind filter $ x -> substring in x
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otherwise => x -> x # nop
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head
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str.split
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tail
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head
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(namedtuple "icepll_config" "feedback filter_range divr divf divq given requested achieved")
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str$ get_field "FEEDBACK"
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int$ get_field "FILTER_RANGE"
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int$ get_field "DIVR"
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int$ get_field "DIVF"
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int$ get_field "DIVQ"
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(*) 1e6 $ float $ get_field "F_PLLIN"
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(*) 1e6 $ float $ get_field "F_PLLOUT" "(requested)"
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(*) 1e6 $ float $ get_field "F_PLLOUT" "(achieved)"
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add_domain_from_pll = platform target_freq domain:"sync" -> pll_config where
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default_clk = platform.request platform.default_clk dir:"-"
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default_freq = platform.default_clk_frequency
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default_reset = if
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platform.default_rst => platform.request platform.default_rst
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otherwise => Const 0
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pll_config = run_icepll
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default_freq
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target_freq
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print pll_config
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pll_clk = Signal!
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pll_lock = Signal!
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Submodule.pll$ Instance "SB_PLL40_PAD" # or "SB_PLL40_CORE"
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i_PACKAGEPIN : default_clk # or i_REFERENCECLK
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i_BYPASS : (Const 0)
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i_RESETB : ~default_reset
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o_LOCK : pll_lock
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o_PLLOUTGLOBAL : pll_clk
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p_FEEDBACK_PATH : pll_config.feedback
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p_FILTER_RANGE : pll_config.filter_range
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p_DIVR : pll_config.divr
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p_DIVF : pll_config.divf
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p_DIVQ : pll_config.divq
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setattr Domains domain (ClockDomain domain)
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Comb$ ClockSignal domain ::= pll_clk
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Submodule.rs$ ResetSynchronizer
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~pll_lock
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domain: domain
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