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Change format for pmod resources

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This commit is contained in:
Peder Bergebakken Sundt 2020-08-08 02:27:31 +02:00
parent f19d68cebd
commit 954b083e89
2 changed files with 38 additions and 31 deletions
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3
fpga/icebreaker.dg
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@ -27,5 +27,6 @@ Top = subclass Elaboratable where
if __name__ == "__main__" =>
plat = ICEBreakerPlatform!
plat.add_resources$ pmod.seven_seg 0 # pmod 1a
plat.add_resources$ pmod.seven_seg pmod: 0 # pmod 1a
plat.add_resources$ pmod.dip_switch8 pmod: 1 # pmod 1b
plat.build Top! do_program: True

66
fpga/resources/pmod.py
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@ -1,36 +1,42 @@
from nmigen.build import *
from functools import partial
__all__ = []
def pmod(func):
__all__.append(func.__name__)
return partial(func,
name = func.__name__,
)
__ALL__ = [
"seven_seg",
]
# Icebreaker PMODs
def seven_seg(pmod_port: int, name="seven_seg"):
conn = ("pmod", pmod_port)
return [
Resource(name, 0,
Subsignal("aa", PinsN( "1", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("ab", PinsN( "2", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("ac", PinsN( "3", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("ad", PinsN( "4", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("ae", PinsN( "7", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("af", PinsN( "8", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("ag", PinsN( "9", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("ca", PinsN("10", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
)
]
Attrs(IO_STANDARD="SB_LVCMOS33")
def dip_switch8(pmod_port: int, name="dip_switch8"):
return [
Resource(name, 0,
Subsignal("d1", PinsN( "1", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("d2", PinsN( "2", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("d3", PinsN( "3", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("d4", PinsN( "4", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("d5", PinsN( "7", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("d5", PinsN( "8", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("d6", PinsN( "9", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
Subsignal("d8", PinsN("10", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
)
]
@pmod
def seven_seg(*, pmod, name = "__name__", number = 0, index = 0, subsignal_args=(), extras={}):
return [Resource(name, number,
Subsignal("aa", PinsN( "1", dir="o", conn=("pmod", pmod)), *subsignal_args),
Subsignal("ab", PinsN( "2", dir="o", conn=("pmod", pmod)), *subsignal_args),
Subsignal("ac", PinsN( "3", dir="o", conn=("pmod", pmod)), *subsignal_args),
Subsignal("ad", PinsN( "4", dir="o", conn=("pmod", pmod)), *subsignal_args),
Subsignal("ae", PinsN( "7", dir="o", conn=("pmod", pmod)), *subsignal_args),
Subsignal("af", PinsN( "8", dir="o", conn=("pmod", pmod)), *subsignal_args),
Subsignal("ag", PinsN( "9", dir="o", conn=("pmod", pmod)), *subsignal_args),
Subsignal("ca", PinsN("10", dir="o", conn=("pmod", pmod)), *subsignal_args),
**extras,
)]
@pmod
def dip_switch8(*, pmod, name = "__name__", number = 0, index = 0, subsignal_args=(), extras={}):
return [Resource(name, number,
Subsignal("d1", PinsN( "1", dir="i", conn=("pmod", pmod)), *subsignal_args),
Subsignal("d2", PinsN( "2", dir="i", conn=("pmod", pmod)), *subsignal_args),
Subsignal("d3", PinsN( "3", dir="i", conn=("pmod", pmod)), *subsignal_args),
Subsignal("d4", PinsN( "4", dir="i", conn=("pmod", pmod)), *subsignal_args),
Subsignal("d5", PinsN( "7", dir="i", conn=("pmod", pmod)), *subsignal_args),
Subsignal("d5", PinsN( "8", dir="i", conn=("pmod", pmod)), *subsignal_args),
Subsignal("d6", PinsN( "9", dir="i", conn=("pmod", pmod)), *subsignal_args),
Subsignal("d8", PinsN("10", dir="i", conn=("pmod", pmod)), *subsignal_args),
**extras,
)]