nmigen-learning/fpga/modules/segment7.dg

60 lines
1.8 KiB
Python

#!/usr/bin/env -S python3 -m dg
import "/nmigen_dg/*"
import "/nmigen/cli/main"
# iCEBreaker 7-Segment Pmod
Segment7x2 = subclass Elaboratable where
__init__ = decimal: True ~> None where
@number = Signal 8 # i
@segs = Signal 7 # o
@select = Signal 1 # o
@decimal = decimal
elaborate = platform ~> m where with m = Module! =>
select = Signal!
Sync$ select :== ~select
seg7 = Submodule$ Segment7!
Comb$ seg7.number :== if
@decimal => Mux select
@number // 10
@number % 10
otherwise => Mux select
@number >> 4
@number & 0x0f
Comb$ @segs :== seg7.segs
Comb$ @select :== select
Segment7 = subclass Elaboratable where
__init__ = self -> None where
@number = Signal 4 # i
@segs = Signal 7 # o
elaborate = platform ~> m where with m = Module! =>
Switch @number
0x0 ,-> Comb$ @segs :== 0b0111111
0x1 ,-> Comb$ @segs :== 0b0000110
0x2 ,-> Comb$ @segs :== 0b1011011
0x3 ,-> Comb$ @segs :== 0b1001111
0x4 ,-> Comb$ @segs :== 0b1100110
0x5 ,-> Comb$ @segs :== 0b1101101
0x6 ,-> Comb$ @segs :== 0b1111101
0x7 ,-> Comb$ @segs :== 0b0000111
0x8 ,-> Comb$ @segs :== 0b1111111
0x9 ,-> Comb$ @segs :== 0b1101111
0xa ,-> Comb$ @segs :== 0b1110111
0xb ,-> Comb$ @segs :== 0b1111100
0xc ,-> Comb$ @segs :== 0b0111001
0xd ,-> Comb$ @segs :== 0b1011110
0xe ,-> Comb$ @segs :== 0b1111001
0xf ,-> Comb$ @segs :== 0b1110001
if __name__ == "__main__" =>
design = Segment7x2!
main design ports: [design.number, design.segs, design.select]