Add common.deduce_ports, improve to_signed

fpga/common.dg

@@ -8,6 +8,13 @@ pipeline = data *: funcs -> data where
         data = func data
 
 # cast to signed, extending the signal by one bit
-to_signed = signal -> out where
+to_signed = signal ->
-    out = Signal$ signed (signal.width + 1)
+    Cat signal 0 |>.as_signed!
-    Comb$ out ::= signal
+
+# only works before any elaboration, assuming ports are defined in __init__
+deduce_ports = elaboratable -> ports where
+    ports = []
+    for name in dir elaboratable =>
+        if not$ name.startswith "_" =>
+            value = getattr elaboratable name
+            value :: Signal => ports.append value