Implement a simple VGA controller
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@ -0,0 +1,185 @@
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#!/usr/bin/env -S python3 -m dg
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import "/nmigen/cli/main"
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import "/nmigen_boards.icebreaker/ICEBreakerPlatform"
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import "/nmigen_dg/*"
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import "/subprocess"
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import "/warnings/warn"
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import "../common/pipeline"
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import "../resources/pmod"
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# total_x = front_x + sync_x + back_x + active_x
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# total_y = front_y + sync_y + back_y + active_x
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# pix_freq = total_x * total_y * fps
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VGA_TIMINGS = dict' # VGA, SVGA, VESA
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#(active_x, active_y, fps), (front_x, sync_x, back_x, front_y, sync_y, back_y)
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( 640, 480, 60), ( 16, 96, 48, 11, 2, 31) # Martin Hinner
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( 640, 480, 72), ( 24, 40, 128, 9, 3, 28) # Martin Hinner
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( 640, 480, 75), ( 16, 96, 48, 11, 2, 32) # Martin Hinner
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( 640, 480, 85), ( 32, 48, 112, 1, 3, 25) # Martin Hinner
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( 640, 1024, 60), ( 24, 56, 124, 1, 3, 38) # Kevin M. Hubbard
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( 800, 480, 45), ( 127, 128, 88, 127, 128, 32) # Kevin M. Hubbard (odd)
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( 800, 600, 56), ( 32, 128, 128, 1, 4, 14) # Martin Hinner
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( 800, 600, 60), ( 40, 128, 88, 1, 4, 23) # Kevin M. Hubbard
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( 800, 600, 60), ( 40, 128, 88, 1, 4, 23) # Martin Hinner
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( 800, 600, 72), ( 56, 120, 64, 37, 6, 23) # Martin Hinner
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( 800, 600, 75), ( 16, 80, 160, 1, 2, 21) # Martin Hinner
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( 800, 600, 85), ( 32, 64, 152, 1, 3, 27) # Martin Hinner
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( 1024, 768, 60), ( 24, 136, 160, 3, 6, 29) # Kevin M. Hubbard
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( 1024, 768, 60), ( 24, 136, 160, 3, 6, 29) # Martin Hinner
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( 1024, 768, 70), ( 24, 136, 144, 3, 6, 29) # Martin Hinner
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( 1024, 768, 75), ( 16, 96, 176, 1, 3, 28) # Martin Hinner
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( 1024, 768, 85), ( 48, 96, 208, 1, 3, 36) # Martin Hinner
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( 1280, 1024, 60), ( 48, 112, 248, 1, 3, 38) # Kevin M. Hubbard
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# https://projectf.io/posts/video-timings-vga-720p-1080p/
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# https://github.com/icebreaker-fpga/icebreaker-examples/blob/master/dvi-12bit/vga_timing.v
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# https://reference.digilentinc.com/learn/programmable-logic/tutorials/vga-display-congroller/start
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# http://tinyvga.com/vga-timing
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# http://martin.hinner.info/vga/timing.html
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# https://linux.die.net/man/1/gtf
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run_gtf = x y fps ->
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out = subprocess.run ["gtf", str x, str y, str fps, "-x"]
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capture_output: True
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check: True
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hr, hss, hse, hfl, vr, vss, vse, vfl = pipeline out.stdout
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bytes.decode
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str.splitlines
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bind map str.strip
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bind filter $ x -> x.startswith "Modeline"
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head
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str.split
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bind drop 3
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bind take 8
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bind map int
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# <--------1--------> <--2--> <--3--> <--4-->
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# _________
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# |-------------------|_______| |_______
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#
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# R SS SE FL
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# 1: visible image
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# 2: blank before sync (aka front porch)
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# 3: sync pulse
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# 4: blank after sync (aka back porch)
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# R: Resolution
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# SS: Sync Start
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# SE: Sync End
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# FL: Frame Length
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#total_x, active_x, front_x, sync_x, back_x = hfl, hr, hss-hr, hse-hss, hfl-hse
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#total_y, active_y, front_y, sync_y, back_y = vfl, vr, vss-vr, vse-vss, vfl-vse
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#print hr hss hse hfl
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#print vr vss vse vfl
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#print active_x front_x sync_x back_x total_x sep:"\t"
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#print active_y front_y sync_y back_y total_x sep:"\t"
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#return (front_x, sync_x, back_x, front_y, sync_y, back_y)
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hss-hr, hse-hss, hfl-hse, vss-vr, vse-vss, vfl-vse
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VgaController = subclass Elaboratable where
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__init__ = x y fps bitwidth resource_name resource_number: 0 ~> None where
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# params
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@resource = (resource_name, resource_number)
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@active_x, @active_y = x, y
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# out
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@pixel_x = Signal$ range @active_x
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@pixel_y = Signal$ range @active_y
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@active = Signal!
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# in
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@r = Signal$ bitwidth
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@g = Signal$ bitwidth
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@b = Signal$ bitwidth
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# derived params
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@front_x, @sync_x, @back_x, @front_y, @sync_y, @back_y = if
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(x, y, fps) in VGA_TIMINGS => VGA_TIMINGS!!(x, y, fps)
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otherwise => run_gtf x y fps
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@total_x = @front_x + @sync_x + @back_x + @active_x
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@total_y = @front_y + @sync_y + @back_y + @active_y
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@pix_freq = @total_x * @total_y * fps
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timings = ~>
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"\n".join$ list'
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("total_x = " + (str @total_x ) |>.ljust 25) + " total_y = " + (str @total_y )
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("front_x = " + (str @front_x ) |>.ljust 25) + " front_y = " + (str @front_y )
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("sync_x = " + (str @sync_x ) |>.ljust 25) + " sync_y = " + (str @sync_y )
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("back_x = " + (str @back_x ) |>.ljust 25) + " back_y = " + (str @back_y )
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("active_x = " + (str @active_x) |>.ljust 25) + " active_y = " + (str @active_y)
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("pix_freq = " + (str @pix_freq))
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elaborate = platform ~> m where with m = Module! =>
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@out = platform.request *: @resource
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# pass along the color data
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Sync$ @out.r :== @r
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Sync$ @out.g :== @g
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Sync$ @out.b :== @b
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# position counters
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counter_x = Signal$ range @total_x
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counter_y = Signal$ range @total_y
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Sync$ counter_x :== counter_x + 1
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When (counter_x == @total_x - 1) $ ->
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Sync$ counter_x :== 0
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Sync$ counter_y :== counter_y + 1
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When (counter_y == @total_y - 1) $ ->
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Sync$ counter_y :== 0
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# drive vga syncs, data enable and user outputs
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Comb$ @pixel_x :== counter_x
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Comb$ @pixel_y :== counter_y
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Sync$ @out.hs :== (&)
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@active_x + @front_x <= counter_x
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counter_x < @active_x + @front_x + @sync_x
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Sync$ @out.vs :== (&)
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@active_y + @front_y <= counter_y
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counter_y < @active_y + @front_y + @sync_y
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Sync$ @out.de :== (&)
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counter_x < @active_x
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counter_y < @active_y
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Comb$ @out.ck :== ClockSignal "sync"
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VgaController3 = bind VgaController
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resource_name: "vga_3bit"
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bitwidth: 1
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VgaController12 = bind VgaController
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resource_name: "vga_12bit"
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bitwidth: 4
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DviController3 = bind VgaController
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resource_name: "dvi_3bit"
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bitwidth: 1
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DviController12 = bind VgaController
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resource_name: "dvi_12bit"
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bitwidth: 4
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if __name__ == "__main__" =>
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plat = ICEBreakerPlatform! # TODO: does there exist any mock platform?
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plat.add_resources$ pmod.dvi_12bit 0
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#design = DviController12 800 480 45
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design = DviController12 800 600 60
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main design plat ports:
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list'
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design.pixel_x
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design.pixel_y
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design.ack
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design.r
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design.g
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design.b
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@ -4,9 +4,7 @@ from functools import partial
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__all__ = []
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__all__ = []
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def pmod(func):
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def pmod(func):
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__all__.append(func.__name__)
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__all__.append(func.__name__)
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return partial(func,
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return partial(func, name=func.__name__)
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name = func.__name__,
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)
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# Icebreaker PMODs
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# Icebreaker PMODs
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@ -14,7 +12,7 @@ def pmod(func):
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#subsignal_args = [Attrs(IO_STANDARD="SB_LVCMOS33")]
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#subsignal_args = [Attrs(IO_STANDARD="SB_LVCMOS33")]
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@pmod
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@pmod
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def seven_seg(number, *, pmod, name = __name__, subsignal_args=(), extras={}):
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def seven_seg(number, *, pmod, name=__name__, subsignal_args=(), extras={}):
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return [Resource(name, number,
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return [Resource(name, number,
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Subsignal("aa", PinsN( "1", dir="o", conn=("pmod", pmod)), *subsignal_args),
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Subsignal("aa", PinsN( "1", dir="o", conn=("pmod", pmod)), *subsignal_args),
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Subsignal("ab", PinsN( "2", dir="o", conn=("pmod", pmod)), *subsignal_args),
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Subsignal("ab", PinsN( "2", dir="o", conn=("pmod", pmod)), *subsignal_args),
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@ -29,7 +27,7 @@ def seven_seg(number, *, pmod, name = __name__, subsignal_args=(), extras={}):
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@pmod
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@pmod
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def dip_switch8(number, *, pmod, name = __name__, subsignal_args=(), extras={}):
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def dip_switch8(number, *, pmod, name=__name__, subsignal_args=(), extras={}):
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return [Resource(name, number,
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return [Resource(name, number,
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Subsignal("d1", PinsN( "1", dir="i", conn=("pmod", pmod)), *subsignal_args),
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Subsignal("d1", PinsN( "1", dir="i", conn=("pmod", pmod)), *subsignal_args),
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Subsignal("d2", PinsN( "2", dir="i", conn=("pmod", pmod)), *subsignal_args),
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Subsignal("d2", PinsN( "2", dir="i", conn=("pmod", pmod)), *subsignal_args),
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@ -41,3 +39,32 @@ def dip_switch8(number, *, pmod, name = __name__, subsignal_args=(), extras={}):
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Subsignal("d8", PinsN("10", dir="i", conn=("pmod", pmod)), *subsignal_args),
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Subsignal("d8", PinsN("10", dir="i", conn=("pmod", pmod)), *subsignal_args),
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**extras,
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**extras,
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)]
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)]
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@pmod
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def dvi_3bit(number, *, pmod1=0, pmod2=1, name=__name__, subsignal_args=(), extras={}):
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return [Resource(name, number,
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Subsignal("r", Pins (" 1", dir="o", conn=("pmod", pmod1)), *subsignal_args), # red
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Subsignal("g", Pins (" 2", dir="o", conn=("pmod", pmod1)), *subsignal_args), # green
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Subsignal("b", Pins (" 3", dir="o", conn=("pmod", pmod2)), *subsignal_args), # blue
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Subsignal("ck", Pins (" 4", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data clock
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Subsignal("de", Pins (" 7", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data enable
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Subsignal("hs", Pins (" 8", dir="o", conn=("pmod", pmod2)), *subsignal_args), # hsync
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Subsignal("vs", Pins (" 9", dir="o", conn=("pmod", pmod2)), *subsignal_args), # vsync
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#Subsignal("", Pins ("10", dir="o", conn=("pmod", pmod2)), *subsignal_args),
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**extras,
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)]
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@pmod
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def dvi_12bit(number, *, pmod1=0, pmod2=1, name=__name__, subsignal_args=(), extras={}):
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return [Resource(name, number,
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Subsignal("r", Pins (" 8 7 2 1", dir="o", conn=("pmod", pmod1)), *subsignal_args), # red
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Subsignal("g", Pins ("10 9 4 3", dir="o", conn=("pmod", pmod1)), *subsignal_args), # green
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Subsignal("b", Pins (" 3 7 8 1", dir="o", conn=("pmod", pmod2)), *subsignal_args), # blue
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Subsignal("ck", Pins (" 2", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data clock
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Subsignal("de", Pins (" 9", dir="o", conn=("pmod", pmod2)), *subsignal_args), # data enable
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Subsignal("hs", PinsN(" 4", dir="o", conn=("pmod", pmod2)), *subsignal_args), # hsync
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Subsignal("vs", Pins ("10", dir="o", conn=("pmod", pmod2)), *subsignal_args), # vsync
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**extras,
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)]
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