pederbs
/
nmigen-learning
1
0
Fork 0
Code Issues Pull Requests Releases Activity

Reduce the amount of lookup tables in Seg7, rename it

This commit is contained in:
Peder Bergebakken Sundt 2020-08-09 22:54:51 +02:00
parent e7d54f249e
commit 546c081521
2 changed files with 26 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
fpga/icebreaker.dg
View File

@ -2,7 +2,7 @@ import "/nmigen_boards.icebreaker/ICEBreakerPlatform"
import "/nmigen_dg/*" import "/nmigen_dg/*"
import "modules/blinker/Blinker" import "modules/blinker/Blinker"
import "modules/pulser/Pulser" import "modules/pulser/Pulser"
import "modules/segment7/Segment7" import "modules/segment7/Segment7x2"
import "resources/pmod" import "resources/pmod"
Top = subclass Elaboratable where Top = subclass Elaboratable where
@ -15,7 +15,7 @@ Top = subclass Elaboratable where
blinker = (Submodule$ Blinker$ freq // 3 ).out blinker = (Submodule$ Blinker$ freq // 3 ).out
pulser = (Submodule$ Pulser$ freq // 10).out pulser = (Submodule$ Pulser$ freq // 10).out
seg7 = Submodule$ Segment7! seg7 = Submodule$ Segment7x2 decimal: True
Comb$ Drive @ledr blinker Comb$ Drive @ledr blinker
@ -26,13 +26,11 @@ Top = subclass Elaboratable where
Comb$ Drive @ledg ff Comb$ Drive @ledg ff
counter = Signal 8 counter = Signal 8
Comb$ Drive seg7.number counter
Comb$ Drive @seg7 seg7.pmod
When pulser $ -> When pulser $ ->
Sync$ Drive ff ~ff
Sync$ Drive counter (counter + 1) Sync$ Drive counter (counter + 1)
Comb$ Drive seg7.number counter
Comb$ Drive @seg7 (Cat seg7.segs seg7.select)
if __name__ == "__main__" => if __name__ == "__main__" =>

43
fpga/modules/segment7.dg
View File

@ -4,38 +4,39 @@ import "/nmigen/cli/main"
# iCEBreaker 7-Segment Pmod # iCEBreaker 7-Segment Pmod
Segment7 = subclass Elaboratable where Segment7x2 = subclass Elaboratable where
__init__ = output_hex: True ~> None where __init__ = decimal: True ~> None where
@number = Signal 8 # i @number = Signal 8 # i
@pmod = Signal 8 # o @segs = Signal 7 # o
@format_hex = output_hex @select = Signal 1 # o
@decimal = decimal
elaborate = platform ~> m where with m = Module! => elaborate = platform ~> m where with m = Module! =>
select = Signal! select = Signal!
Sync$ Drive select ~select Sync$ Drive select ~select
s1 = Submodule$ Digit2Segs! seg7 = Submodule$ Segment7!
s2 = Submodule$ Digit2Segs!
if @format_hex => if not @decimal =>
Comb$ Drive s1.digit $ @number >> 4 Comb$ Drive seg7.number $ Mux select
Comb$ Drive s2.digit $ @number & 0x0f @number >> 4
if not @format_hex => @number & 0x0f
Comb$ Drive s1.digit $ @number // 10 if @decimal =>
Comb$ Drive s2.digit $ @number & 10 Comb$ Drive seg7.number $ Mux select
@number // 10
@number % 10
Comb$ Drive @pmod $ Cat Comb$ Drive @segs seg7.segs
Mux select s1.segs s2.segs Comb$ Drive @select select
select
Digit2Segs = subclass Elaboratable where Segment7 = subclass Elaboratable where
__init__ = self -> None where __init__ = self -> None where
@digit = Signal 4 @number = Signal 4 # i
@segs = Signal 7 @segs = Signal 7 # o
elaborate = platform ~> m where with m = Module! => elaborate = platform ~> m where with m = Module! =>
Switch self.digit Switch @number
0x0 ,-> Comb$ Drive @segs 0b0111111 0x0 ,-> Comb$ Drive @segs 0b0111111
0x1 ,-> Comb$ Drive @segs 0b0000110 0x1 ,-> Comb$ Drive @segs 0b0000110
0x2 ,-> Comb$ Drive @segs 0b1011011 0x2 ,-> Comb$ Drive @segs 0b1011011
@ -55,5 +56,5 @@ Digit2Segs = subclass Elaboratable where
if __name__ == "__main__" => if __name__ == "__main__" =>
design = Seg7! design = Segment7x2!
main design ports: [design.pmod] main design ports: [design.number, design.segs, design.select]