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multiply frequency output from icepll by 1e6

This commit is contained in:
Peder Bergebakken Sundt 2020-08-16 23:42:45 +02:00
parent f10086c84b
commit 31894085ff
1 changed files with 3 additions and 3 deletions
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6
fpga/icebreaker_vga.dg
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@ -34,9 +34,9 @@ run_icepll = current target ->
int$ get_field "DIVR"
int$ get_field "DIVF"
int$ get_field "DIVQ"
float$ get_field "F_PLLIN"
float$ get_field "F_PLLOUT" "(requested)"
float$ get_field "F_PLLOUT" "(achieved)"
(*) 1e6 $ float $ get_field "F_PLLIN"
(*) 1e6 $ float $ get_field "F_PLLOUT" "(requested)"
(*) 1e6 $ float $ get_field "F_PLLOUT" "(achieved)"
Top = subclass Elaboratable where