52 lines
1.8 KiB
Plaintext
52 lines
1.8 KiB
Plaintext
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import "/nmigen/lib/cdc/ResetSynchronizer"
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import "/nmigen_boards.icebreaker/ICEBreakerPlatform"
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import "/nmigen_dg/*"
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import "/sys"
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import "resources/pmod"
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Top = subclass Elaboratable where
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elaborate = platform ~> m where with m = Module! =>
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reset = if
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platform.default_rst => platform.request platform.default_rst
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otherwise => Const 0
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# setup clock
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clk40 = Signal!
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pll_lock = Signal!
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Submodule.pll$ Instance "SB_PLL40_PAD" # "SB_PLL40_CORE"
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i_PACKAGEPIN : (platform.request "clk12" dir:"-") # i_REFERENCECLK
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i_BYPASS : (Const 0)
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i_RESETB : ~reset
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o_LOCK : pll_lock
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o_PLLOUTGLOBAL : clk40
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# icepll -o 40
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p_FEEDBACK_PATH : "SIMPLE"
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p_FILTER_RANGE : 1
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p_DIVR : 0
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p_DIVF : 52
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p_DIVQ : 4
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#m.domains.sync = ClockDomain "sync"
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Domains.sync = ClockDomain "sync"
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Comb$ ClockSignal "sync" :== clk40
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Submodule$ ResetSynchronizer ~pll_lock domain: "sync"
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state = Signal!
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counter = Signal$ range (int plat.default_clk_frequency)
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Sync$ counter :== counter - 1
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When (counter==0) $ ->
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Sync$ counter :== (int plat.default_clk_frequency)
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Sync$ state :== ~state
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Comb$ platform.request "led_r" :== state # blinks at 1hz with default clk, but way faster when at 40MHz
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Comb$ platform.request "led_g" :== ~state # blinks at 1hz with default clk, but way faster when at 40MHz
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if __name__ == "__main__" =>
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plat = ICEBreakerPlatform!
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plat.add_resources$ pmod.dvi_12bit 0
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plat.add_resources$ plat.break_off_pmod
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plat.build Top! do_program: ("--flash" in sys.argv)
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