nmigen-learning/fpga/common.dg

import "/nmigen_dg/*"

# result = pipeline 5
#     bind (+) 1
#     bind (-) 5
pipeline = data *: funcs -> data where
    for func in funcs =>
        data = func data

# cast to signed, extending the signal by one bit
to_signed = signal ->
    Cat signal 0 |>.as_signed!

# only works before any elaboration, assuming ports are defined in __init__
deduce_ports = elaboratable -> ports where
    ports = []
    for name in dir elaboratable =>
        if not$ name.startswith "_" =>
            value = getattr elaboratable name
            value :: Signal => ports.append value