diff --git a/fpga/icebreaker.dg b/fpga/icebreaker.dg
index 3a620dd..f644cc0 100644
--- a/fpga/icebreaker.dg
+++ b/fpga/icebreaker.dg
@@ -2,6 +2,7 @@ import "/nmigen_boards.icebreaker/ICEBreakerPlatform"
 import "/nmigen_dg/*"
 import "modules/Blinker"
 import "modules/Pulser"
+import "resources/pmod"
 
 Top = subclass Elaboratable where
     elaborate = platform ~> m where with m = Module! =>
@@ -9,6 +10,7 @@ Top = subclass Elaboratable where
 
         @ledr = platform.request "led_r"
         @ledg = platform.request "led_g"
+        @seg7 = platform.request "seven_seg"
 
         blinker1 = Blinker$ int (freq // 3)
         m.submodules += blinker1
@@ -25,4 +27,5 @@ Top = subclass Elaboratable where
 
 if __name__ == "__main__" =>
     plat = ICEBreakerPlatform!
+    plat.add_resources$ pmod.seven_seg 0 # pmod 1a
     plat.build Top! do_program: True
diff --git a/fpga/resources/__init__.py b/fpga/resources/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/fpga/resources/pmod.py b/fpga/resources/pmod.py
new file mode 100644
index 0000000..235ca36
--- /dev/null
+++ b/fpga/resources/pmod.py
@@ -0,0 +1,36 @@
+from nmigen.build import *
+
+__ALL__ = [
+    "seven_seg",
+]
+
+# Icebreaker PMODs
+
+def seven_seg(pmod_port: int, name="seven_seg"):
+    conn = ("pmod", pmod_port)
+    return [
+        Resource(name, 0,
+             Subsignal("aa", PinsN( "1", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("ab", PinsN( "2", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("ac", PinsN( "3", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("ad", PinsN( "4", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("ae", PinsN( "7", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("af", PinsN( "8", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("ag", PinsN( "9", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("ca", PinsN("10", dir="o", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+         )
+    ]
+
+def dip_switch8(pmod_port: int, name="dip_switch8"):
+    return [
+        Resource(name, 0,
+             Subsignal("d1", PinsN( "1", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("d2", PinsN( "2", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("d3", PinsN( "3", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("d4", PinsN( "4", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("d5", PinsN( "7", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("d5", PinsN( "8", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("d6", PinsN( "9", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+             Subsignal("d8", PinsN("10", dir="i", conn=conn), Attrs(IO_STANDARD="SB_LVCMOS33")),
+         )
+    ]