From c68ec0f876ca04939ebac354f0ca0c0fb150353c Mon Sep 17 00:00:00 2001
From: Peder Bergebakken Sundt <pbsds@hotmail.com>
Date: Sun, 9 Aug 2020 21:55:44 +0200
Subject: [PATCH] split blinker into blinker and pulser

---
 fpga/icebreaker.dg      |  2 +-
 fpga/modules/blinker.dg | 22 ++++++----------------
 fpga/modules/pulser.dg  | 21 +++++++++++++++++++++
 3 files changed, 28 insertions(+), 17 deletions(-)
 create mode 100644 fpga/modules/pulser.dg

diff --git a/fpga/icebreaker.dg b/fpga/icebreaker.dg
index 13c011e..0f0f471 100644
--- a/fpga/icebreaker.dg
+++ b/fpga/icebreaker.dg
@@ -1,7 +1,7 @@
 import "/nmigen_boards.icebreaker/ICEBreakerPlatform"
 import "/nmigen_dg/*"
 import "modules/blinker/Blinker"
-import "modules/blinker/Pulser"
+import "modules/pulser/Pulser"
 import "resources/pmod"
 
 Top = subclass Elaboratable where
diff --git a/fpga/modules/blinker.dg b/fpga/modules/blinker.dg
index 573d45c..0ae5372 100644
--- a/fpga/modules/blinker.dg
+++ b/fpga/modules/blinker.dg
@@ -2,28 +2,18 @@ import "/nmigen/cli/main"
 import "/nmigen_dg/*"
 
 Blinker = subclass Elaboratable where
-    __init__ = ncycles pulse: False ~> None where
+    __init__ = ncycles ~> None where
         @ncycles = ncycles
-        @pulse = pulse
         @out = Signal!
 
     elaborate = platform ~> m where with m = Module! =>
         counter = Signal$ range (@ncycles + 1)
+        Sync$ Drive counter (counter - 1)
 
-        if @pulse =>
-            sync$ drive @out LOW
-
-        when
-            counter == 0 ,->
-                sync$ drive @out  (~ @out)
-                sync$ drive counter @ncycles
-            otherwise ,->
-                sync$ drive counter (counter - 1)
-
-
-Pulser = bind Blinker pulse: True
-
+        When (counter == 0) $ ->
+            Sync$ Drive @out (~ @out)
+            Sync$ Drive counter @ncycles
 
 if __name__ == "__main__" =>
     blinker = Blinker ncycles: 10000000
-    main blinker ports: [blinker.out]
+    main blinker name: "blinker" ports: [blinker.out]
diff --git a/fpga/modules/pulser.dg b/fpga/modules/pulser.dg
new file mode 100644
index 0000000..91b960a
--- /dev/null
+++ b/fpga/modules/pulser.dg
@@ -0,0 +1,21 @@
+import "/nmigen/cli/main"
+import "/nmigen_dg/*"
+
+Pulser = subclass Elaboratable where
+    __init__ = ncycles ~> None where
+        @ncycles = ncycles
+        @out = Signal!
+
+    elaborate = platform ~> m where with m = Module! =>
+        Sync$ Drive @out LOW
+
+        counter = Signal$ range (@ncycles + 1)
+        Sync$ Drive counter (counter - 1)
+
+        When (counter == 0) $ ->
+            Sync$ Drive @out HIGH
+            Sync$ Drive counter @ncycles
+
+if __name__ == "__main__" =>
+    pulser = Pulser ncycles: 10000000
+    main pulser name: "pulser" ports: [pulser.out]