From a3721512cbacdcf0ff1890908f40a3d8e5502795 Mon Sep 17 00:00:00 2001 From: Peder Bergebakken Sundt Date: Sun, 16 Aug 2020 23:30:36 +0200 Subject: [PATCH] Make the picture generated more fancy --- fpga/icebreaker_vga.dg | 37 ++++++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/fpga/icebreaker_vga.dg b/fpga/icebreaker_vga.dg index ffe723a..4003372 100644 --- a/fpga/icebreaker_vga.dg +++ b/fpga/icebreaker_vga.dg @@ -80,27 +80,38 @@ Top = subclass Elaboratable where domain: "sync" - # Simple test to see if the PLL works - state = Signal! - counter = Signal$ range (int plat.default_clk_frequency) + # Feed a picture to the DVI controller + + scroll = Signal 8 + + period = int (pll_config.achieved / 60) + counter = Signal$ range period Sync$ counter :== counter - 1 When (counter==0) $ -> - Sync$ counter :== int plat.default_clk_frequency - Sync$ state :== ~state - Comb$ platform.request "led_r" :== state - Comb$ platform.request "led_g" :== ~state + Sync$ counter :== int period + Sync$ scroll :== scroll + 1 - - # Feed a pciture to the DVI controller Sync$ dvi.r :== 0x0 Sync$ dvi.g :== 0x0 Sync$ dvi.b :== 0x0 cx = to_signed dvi.pixel_x - (800//2) cy = to_signed dvi.pixel_y - (480//2) - When (cx*cx + cy*cy < 150**2) $ -> - Sync$ dvi.r :== 0xF - Sync$ dvi.g :== 0xF - Sync$ dvi.b :== 0xF + rx = cx*cx + ry = cy*cy + tx1 = (dvi.pixel_x - scroll) & (1<<5) + ty1 = (dvi.pixel_y - scroll) & (1<<5) + tx2 = (dvi.pixel_x + scroll) & (1<<6) + ty2 = (dvi.pixel_y + scroll + 40) & (1<<6) + When + rx + ry < 200**2 ,-> + Sync$ dvi.r :== 0xF + #Sync$ dvi.g :== 0xF + Sync$ dvi.b :== 0xF + tx1 ^ ty1 ,-> + Sync$ dvi.b :== 0xF + tx2 ^ ty2 ,-> + Sync$ dvi.r :== 0xF + Sync$ dvi.g :== 0xF if __name__ == "__main__" =>