diff --git a/README.md b/README.md
index 2a7735c..d7e8b8e 100644
--- a/README.md
+++ b/README.md
@@ -9,7 +9,7 @@ My focus is currently on:
 	* Effortless dependency management
 	* Helper functions for inspection and documentation of the design
 	* Helper functions for targeting multiple FPGA platforms and boards
-	* Creating PRs to other projects with stuff i find here
+	* Creating PRs to other projects with stuff I come across here
 	* Having fun with my FPGA
 
 # Setup
@@ -38,8 +38,8 @@ To reduce the amount of typing:
 
 * Diagrams are nice
 * Documentation generation would be nice
-* A central nmigen-pmod library would be nice
+* A central nmigen-pmod repository would be nice
 * A RISCV toolchain would be nice (make socs, and compile C, C++ or Rust)
-* nextpnr-xray or vtr would be nice
+* nextpnr-prxray or vpr would be nice
 * Batch setup of Vivado would be nice
 * Ability to synth on a host accessible with ssh would be nice
diff --git a/fpga/icebreaker_vga.dg b/fpga/icebreaker_vga.dg
index c364eee..47a2cb2 100644
--- a/fpga/icebreaker_vga.dg
+++ b/fpga/icebreaker_vga.dg
@@ -19,6 +19,7 @@ Top = subclass Elaboratable where
 
         # setup clock
         pll_config = add_domain_from_pll platform dvi.pix_freq
+        print pll_config
 
 
         # Feed a picture to the DVI controller
diff --git a/fpga/modules/vga.dg b/fpga/modules/vga.dg
index 4af020d..6bf4743 100644
--- a/fpga/modules/vga.dg
+++ b/fpga/modules/vga.dg
@@ -56,7 +56,7 @@ VGA_TIMINGS = dict' # VGA, SVGA, VESA
 # http://martin.hinner.info/vga/timing.html
 
 
-run_gtf = x y fps ->
+run_gtf = x y fps -> # TODO: pack this dependency with wasmtime?
     out = subprocess.run ["gtf", str x, str y, str fps, "-x"]
         capture_output: True
         check: True
@@ -86,6 +86,8 @@ VgaController = subclass Elaboratable where
         @pixel_x = Signal$ range @active_x
         @pixel_y = Signal$ range @active_y
         @active  = Signal!
+        @hblank_begin = Signal! # pulsed at start of hblank
+        @vblank_begin = Signal! # pulsed at start of vblank
 
         # in
         @r = Signal$ bitwidth
@@ -113,9 +115,9 @@ VgaController = subclass Elaboratable where
         @out = platform.request *: @resource
 
         # pass along the color data
-        Sync$ @out.r ::= @r
-        Sync$ @out.g ::= @g
-        Sync$ @out.b ::= @b
+        Comb$ @out.r ::= @r
+        Comb$ @out.g ::= @g
+        Comb$ @out.b ::= @b
 
         # position counters
         counter_x = Signal$ range @total_x
@@ -127,6 +129,9 @@ VgaController = subclass Elaboratable where
             When (counter_y == @total_y - 1) $ ->
                 Sync$ counter_y ::= 0
 
+        Sync$ @hblank_begin ::= ((counter_x == @active_x))
+        Sync$ @vblank_begin ::= ((counter_x == @active_x) & (counter_y == @active_y - 1))
+
         # drive vga syncs, data enable and user outputs
         Comb$ @pixel_x ::= counter_x
         Comb$ @pixel_y ::= counter_y
diff --git a/fpga/stdio/ice40pll.dg b/fpga/stdio/ice40pll.dg
index 7c72e40..ec9141e 100644
--- a/fpga/stdio/ice40pll.dg
+++ b/fpga/stdio/ice40pll.dg
@@ -4,7 +4,7 @@ import "/nmigen_dg/*"
 import "/subprocess"
 import "../common/pipeline"
 
-run_icepll = current target ->
+run_icepll = current target -> # TODO: use yowasp-nextpnr-ice40 if installed
     current /= 1e6 # Hz -> MHz
     target  /= 1e6 # Hz -> MHz
     out = subprocess.run ["icepll", "-i", str current, "-o", str target]
@@ -44,7 +44,6 @@ add_domain_from_pll = platform target_freq domain:"sync" -> pll_config where
     pll_config = run_icepll
         default_freq
         target_freq
-    print pll_config
 
     pll_clk  = Signal!
     pll_lock = Signal!