From 3dacf1eb90378976b8cfc18416522ce6494d775a Mon Sep 17 00:00:00 2001
From: Peder Bergebakken Sundt <pbsds@hotmail.com>
Date: Thu, 6 Aug 2020 23:33:19 +0200
Subject: [PATCH] Implement a simple blinker

Reimplemented the icebreaker top in nmigen_dg
---
 fpga/icebreaker.dg       | 28 ++++++++++++++++++++++++++++
 fpga/icebreaker.py       | 28 ----------------------------
 fpga/modules/__init__.py |  2 ++
 fpga/modules/blinker.dg  | 29 +++++++++++++++++++++++++++++
 4 files changed, 59 insertions(+), 28 deletions(-)
 create mode 100644 fpga/icebreaker.dg
 delete mode 100644 fpga/icebreaker.py
 create mode 100644 fpga/modules/__init__.py
 create mode 100644 fpga/modules/blinker.dg

diff --git a/fpga/icebreaker.dg b/fpga/icebreaker.dg
new file mode 100644
index 0000000..3a620dd
--- /dev/null
+++ b/fpga/icebreaker.dg
@@ -0,0 +1,28 @@
+import "/nmigen_boards.icebreaker/ICEBreakerPlatform"
+import "/nmigen_dg/*"
+import "modules/Blinker"
+import "modules/Pulser"
+
+Top = subclass Elaboratable where
+    elaborate = platform ~> m where with m = Module! =>
+        freq = int platform.default_clk_frequency
+
+        @ledr = platform.request "led_r"
+        @ledg = platform.request "led_g"
+
+        blinker1 = Blinker$ int (freq // 3)
+        m.submodules += blinker1
+
+        blinker2 = Pulser$ int (freq // 3)
+        m.submodules += blinker2
+
+        comb$ drive @ledr blinker1.out
+
+        hello = Signal 1 reset: 1
+        when blinker2.out $ ->
+            sync$ drive hello ~hello
+        sync$ drive @ledg hello
+
+if __name__ == "__main__" =>
+    plat = ICEBreakerPlatform!
+    plat.build Top! do_program: True
diff --git a/fpga/icebreaker.py b/fpga/icebreaker.py
deleted file mode 100644
index 0b50e97..0000000
--- a/fpga/icebreaker.py
+++ /dev/null
@@ -1,28 +0,0 @@
-from nmigen import *
-from nmigen.cli import main
-from nmigen_boards.icebreaker import ICEBreakerPlatform
-
-class Blinker(Elaboratable):
-    def __init__(self, maxperiod: int):
-        self.maxperiod = maxperiod
-
-    def elaborate(self, platform):
-        led = platform.request("led_r")
-
-        m = Module()
-
-        counter = Signal(range(self.maxperiod + 1))
-
-        with m.If(counter == 0):
-            m.d.sync += led.eq(~led)
-            m.d.sync += counter.eq(self.maxperiod)
-        with m.Else():
-            m.d.sync += counter.eq(counter - 1)
-
-        return m
-
-if __name__ == "__main__":
-    plat = ICEBreakerPlatform()
-    #main(plat, ports=[plat.led])
-    plat.build(Blinker(10000000), do_program=True)
-
diff --git a/fpga/modules/__init__.py b/fpga/modules/__init__.py
new file mode 100644
index 0000000..0c32022
--- /dev/null
+++ b/fpga/modules/__init__.py
@@ -0,0 +1,2 @@
+from .blinker import Blinker
+from .blinker import Pulser
diff --git a/fpga/modules/blinker.dg b/fpga/modules/blinker.dg
new file mode 100644
index 0000000..573d45c
--- /dev/null
+++ b/fpga/modules/blinker.dg
@@ -0,0 +1,29 @@
+import "/nmigen/cli/main"
+import "/nmigen_dg/*"
+
+Blinker = subclass Elaboratable where
+    __init__ = ncycles pulse: False ~> None where
+        @ncycles = ncycles
+        @pulse = pulse
+        @out = Signal!
+
+    elaborate = platform ~> m where with m = Module! =>
+        counter = Signal$ range (@ncycles + 1)
+
+        if @pulse =>
+            sync$ drive @out LOW
+
+        when
+            counter == 0 ,->
+                sync$ drive @out  (~ @out)
+                sync$ drive counter @ncycles
+            otherwise ,->
+                sync$ drive counter (counter - 1)
+
+
+Pulser = bind Blinker pulse: True
+
+
+if __name__ == "__main__" =>
+    blinker = Blinker ncycles: 10000000
+    main blinker ports: [blinker.out]