diff --git a/fpga/common.dg b/fpga/common.dg index 7257d4e..5ae5d1a 100644 --- a/fpga/common.dg +++ b/fpga/common.dg @@ -10,4 +10,4 @@ pipeline = data *: funcs -> data where # cast to signed, extending the signal by one bit to_signed = signal -> out where out = Signal$ signed (signal.width + 1) - Comb$ out :== signal + Comb$ out ::= signal diff --git a/fpga/icebreaker.dg b/fpga/icebreaker.dg index cf3ce5a..5b27af9 100644 --- a/fpga/icebreaker.dg +++ b/fpga/icebreaker.dg @@ -18,17 +18,17 @@ Top = subclass Elaboratable where pulser = (Submodule.pulser $ Pulser$ freq // 2).out seg7 = Submodule.seg7$ Segment7x2 decimal: False - Comb$ @ledr :== blinker + Comb$ @ledr ::= blinker ff = Signal 1 reset: 1 When pulser $ -> - Sync$ ff :== ~ff + Sync$ ff ::= ~ff - Comb$ @ledg :== ff + Comb$ @ledg ::= ff counter = Signal 4 When pulser $ -> - Sync$ counter :== counter + 1 + Sync$ counter ::= counter + 1 # TODO: learn SPI FLASH mem = Memory @@ -36,13 +36,13 @@ Top = subclass Elaboratable where depth: 16 # ew init: ([0xde, 0xad, 0xbe, 0xef]*4) rdport = Submodule.rdport$ mem.read_port! - Comb$ rdport.addr :== counter + Comb$ rdport.addr ::= counter - Comb$ seg7.number :== rdport.data - #Comb$ seg7.number :== counter - Comb$ @seg7 :== Cat seg7.segs seg7.select + Comb$ seg7.number ::= rdport.data + #Comb$ seg7.number ::= counter + Comb$ @seg7 ::= Cat seg7.segs seg7.select @@ -57,20 +57,20 @@ Top = subclass Elaboratable where @btn_l = platform.request "button" 3 state = Signal 4 reset: 0b1000 - Comb$ @leds :== state - Comb$ @ledm :== (@btn_r | @btn_l) + Comb$ @leds ::= state + Comb$ @ledm ::= (@btn_r | @btn_l) When (on_rising_edge @btn_l) $ -> - Sync$ state :== state.rotate_left 1 + Sync$ state ::= state.rotate_left 1 When (on_rising_edge @btn_r) $ -> - Sync$ state :== state.rotate_right 1 + Sync$ state ::= state.rotate_right 1 When (on_rising_edge @btn_m) $ -> - Sync$ state :== ~state + Sync$ state ::= ~state on_rising_edge = signal -> result where prev = Signal (signal.shape!) - Sync$ prev :== signal + Sync$ prev ::= signal result = ~ signal.implies prev diff --git a/fpga/icebreaker_vga.dg b/fpga/icebreaker_vga.dg index bcfa6a9..9ea5ccb 100644 --- a/fpga/icebreaker_vga.dg +++ b/fpga/icebreaker_vga.dg @@ -77,7 +77,7 @@ Top = subclass Elaboratable where p_DIVQ : pll_config.DIVQ Domains.sync = ClockDomain "sync" - Comb$ ClockSignal "sync" :== pll_clk + Comb$ ClockSignal "sync" ::= pll_clk Submodule.rs$ ResetSynchronizer ~pll_lock @@ -90,14 +90,14 @@ Top = subclass Elaboratable where period = int (pll_config.achieved / 60) counter = Signal$ range period - Sync$ counter :== counter - 1 + Sync$ counter ::= counter - 1 When (counter==0) $ -> - Sync$ counter :== int period - Sync$ scroll :== scroll + 1 + Sync$ counter ::= int period + Sync$ scroll ::= scroll + 1 - Sync$ dvi.r :== 0x0 - Sync$ dvi.g :== 0x0 - Sync$ dvi.b :== 0x0 + Sync$ dvi.r ::= 0x0 + Sync$ dvi.g ::= 0x0 + Sync$ dvi.b ::= 0x0 cx = to_signed dvi.pixel_x - (@x // 2) cy = to_signed dvi.pixel_y - (@y // 2) rx = cx*cx @@ -108,14 +108,14 @@ Top = subclass Elaboratable where ty2 = (dvi.pixel_y + scroll + 40) & (1<<6) When rx + ry < 200**2 ,-> - Sync$ dvi.r :== 0xF - #Sync$ dvi.g :== 0xF - Sync$ dvi.b :== 0xF + Sync$ dvi.r ::= 0xF + #Sync$ dvi.g ::= 0xF + Sync$ dvi.b ::= 0xF tx1 ^ ty1 ,-> - Sync$ dvi.b :== 0xF + Sync$ dvi.b ::= 0xF tx2 ^ ty2 ,-> - Sync$ dvi.r :== 0xF - Sync$ dvi.g :== 0xF + Sync$ dvi.r ::= 0xF + Sync$ dvi.g ::= 0xF if __name__ == "__main__" => diff --git a/fpga/modules/blinker.dg b/fpga/modules/blinker.dg index ebbc5de..1a5e620 100644 --- a/fpga/modules/blinker.dg +++ b/fpga/modules/blinker.dg @@ -8,11 +8,11 @@ Blinker = subclass Elaboratable where elaborate = platform ~> m where with m = Module! => counter = Signal$ range (@ncycles + 1) - Sync$ counter :== counter - 1 + Sync$ counter ::= counter - 1 When (counter == 0) $ -> - Sync$ @out :== ~ @out - Sync$ counter :== @ncycles + Sync$ @out ::= ~ @out + Sync$ counter ::= @ncycles if __name__ == "__main__" => blinker = Blinker ncycles: 10000000 diff --git a/fpga/modules/pulser.dg b/fpga/modules/pulser.dg index 2aa8d80..37ab121 100644 --- a/fpga/modules/pulser.dg +++ b/fpga/modules/pulser.dg @@ -7,14 +7,14 @@ Pulser = subclass Elaboratable where @out = Signal! elaborate = platform ~> m where with m = Module! => - Sync$ @out :== 0 + Sync$ @out ::= 0 counter = Signal$ range (@ncycles + 1) - Sync$ counter :== counter - 1 + Sync$ counter ::= counter - 1 When (counter == 0) $ -> - Sync$ @out :== HIGH - Sync$ counter :== @ncycles + Sync$ @out ::= HIGH + Sync$ counter ::= @ncycles if __name__ == "__main__" => pulser = Pulser ncycles: 10000000 diff --git a/fpga/modules/segment7.dg b/fpga/modules/segment7.dg index f959aeb..bda6181 100644 --- a/fpga/modules/segment7.dg +++ b/fpga/modules/segment7.dg @@ -13,11 +13,11 @@ Segment7x2 = subclass Elaboratable where elaborate = platform ~> m where with m = Module! => select = Signal! - Sync$ select :== ~select + Sync$ select ::= ~select seg7 = Submodule$ Segment7! - Comb$ seg7.number :== if + Comb$ seg7.number ::= if @decimal => Mux select @number // 10 @number % 10 @@ -25,8 +25,8 @@ Segment7x2 = subclass Elaboratable where @number >> 4 @number & 0x0f - Comb$ @segs :== seg7.segs - Comb$ @select :== select + Comb$ @segs ::= seg7.segs + Comb$ @select ::= select Segment7 = subclass Elaboratable where @@ -36,22 +36,22 @@ Segment7 = subclass Elaboratable where elaborate = platform ~> m where with m = Module! => Switch @number - 0x0 ,-> Comb$ @segs :== 0b0111111 - 0x1 ,-> Comb$ @segs :== 0b0000110 - 0x2 ,-> Comb$ @segs :== 0b1011011 - 0x3 ,-> Comb$ @segs :== 0b1001111 - 0x4 ,-> Comb$ @segs :== 0b1100110 - 0x5 ,-> Comb$ @segs :== 0b1101101 - 0x6 ,-> Comb$ @segs :== 0b1111101 - 0x7 ,-> Comb$ @segs :== 0b0000111 - 0x8 ,-> Comb$ @segs :== 0b1111111 - 0x9 ,-> Comb$ @segs :== 0b1101111 - 0xa ,-> Comb$ @segs :== 0b1110111 - 0xb ,-> Comb$ @segs :== 0b1111100 - 0xc ,-> Comb$ @segs :== 0b0111001 - 0xd ,-> Comb$ @segs :== 0b1011110 - 0xe ,-> Comb$ @segs :== 0b1111001 - 0xf ,-> Comb$ @segs :== 0b1110001 + 0x0 ,-> Comb$ @segs ::= 0b0111111 + 0x1 ,-> Comb$ @segs ::= 0b0000110 + 0x2 ,-> Comb$ @segs ::= 0b1011011 + 0x3 ,-> Comb$ @segs ::= 0b1001111 + 0x4 ,-> Comb$ @segs ::= 0b1100110 + 0x5 ,-> Comb$ @segs ::= 0b1101101 + 0x6 ,-> Comb$ @segs ::= 0b1111101 + 0x7 ,-> Comb$ @segs ::= 0b0000111 + 0x8 ,-> Comb$ @segs ::= 0b1111111 + 0x9 ,-> Comb$ @segs ::= 0b1101111 + 0xa ,-> Comb$ @segs ::= 0b1110111 + 0xb ,-> Comb$ @segs ::= 0b1111100 + 0xc ,-> Comb$ @segs ::= 0b0111001 + 0xd ,-> Comb$ @segs ::= 0b1011110 + 0xe ,-> Comb$ @segs ::= 0b1111001 + 0xf ,-> Comb$ @segs ::= 0b1110001 if __name__ == "__main__" => diff --git a/fpga/modules/vga.dg b/fpga/modules/vga.dg index 6e843a1..b488232 100644 --- a/fpga/modules/vga.dg +++ b/fpga/modules/vga.dg @@ -119,34 +119,34 @@ VgaController = subclass Elaboratable where @out = platform.request *: @resource # pass along the color data - Sync$ @out.r :== @r - Sync$ @out.g :== @g - Sync$ @out.b :== @b + Sync$ @out.r ::= @r + Sync$ @out.g ::= @g + Sync$ @out.b ::= @b # position counters counter_x = Signal$ range @total_x counter_y = Signal$ range @total_y - Sync$ counter_x :== counter_x + 1 + Sync$ counter_x ::= counter_x + 1 When (counter_x == @total_x - 1) $ -> - Sync$ counter_x :== 0 - Sync$ counter_y :== counter_y + 1 + Sync$ counter_x ::= 0 + Sync$ counter_y ::= counter_y + 1 When (counter_y == @total_y - 1) $ -> - Sync$ counter_y :== 0 + Sync$ counter_y ::= 0 # drive vga syncs, data enable and user outputs - Comb$ @pixel_x :== counter_x - Comb$ @pixel_y :== counter_y - Sync$ @out.hs :== (&) + Comb$ @pixel_x ::= counter_x + Comb$ @pixel_y ::= counter_y + Sync$ @out.hs ::= (&) @active_x + @front_x <= counter_x counter_x < @active_x + @front_x + @sync_x - Sync$ @out.vs :== (&) + Sync$ @out.vs ::= (&) @active_y + @front_y <= counter_y counter_y < @active_y + @front_y + @sync_y - Sync$ @out.de :== (&) + Sync$ @out.de ::= (&) counter_x < @active_x counter_y < @active_y - Comb$ @out.ck :== ClockSignal "sync" + Comb$ @out.ck ::= ClockSignal "sync"